| Property | Value |
| Project Name: | e:\hdl\fndisework\spartan3_starter_kit\dynadisp_test\dynadisp_test |
| Target Device: | xc3s200 |
| Report Generated: | Wednesday 10/26/05 at 16:35 |
| Printable Summary (View as HTML) | dynadisp_test_summary.html |
| Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Flip Flops: | 22 | 3,840 | 1% | |
| Number of 4 input LUTs: | 38 | 3,840 | 1% | |
| Logic Distribution: | ||||
| Number of occupied Slices: | 26 | 1,920 | 1% | |
| Number of Slices containing only related logic: | 26 | 26 | 100% | |
| Number of Slices containing unrelated logic: | 0 | 26 | 0% | |
| Total Number 4 input LUTs: | 44 | 3,840 | 1% | |
| Number used as logic: | 38 | |||
| Number used as a route-thru: | 6 | |||
| Number of bonded IOBs: | 19 | 173 | 10% | |
| Number of GCLKs: | 1 | 8 | 12% |
| Property | Value |
| Final Timing Score: | 0 |
| Number of Unrouted Signals: | All signals are completely routed. |
| Number of Failing Constraints: | 0 |
| Constraint(s) | Requested | Actual | Logic Levels |
| All Constraints Met |
| Report Name | Status | Last Date Modified |
| Synthesis Report | Current | Wednesday 10/26/05 at 16:35 |
| Translation Report | Current | Wednesday 10/26/05 at 16:35 |
| Map Report | Current | Wednesday 10/26/05 at 16:35 |
| Pad Report | Current | Wednesday 10/26/05 at 16:35 |
| Place and Route Report | Current | Wednesday 10/26/05 at 16:35 |
| Post Place and Route Static Timing Report | Current | Wednesday 10/26/05 at 16:35 |
| Bitgen Report | Current | Wednesday 10/26/05 at 16:35 |