NET "sysclk" IOSTANDARD = LVCMOS33;
NET "sysclk" LOC = E12;
NET "ddr2_address[12]" IOSTANDARD = SSTL18_II;
NET "ddr2_address[12]" LOC = Y2;
NET "ddr2_address[11]" IOSTANDARD = SSTL18_II;
NET "ddr2_address[11]" LOC = V1;
NET "ddr2_address[10]" IOSTANDARD = SSTL18_II;
NET "ddr2_address[10]" LOC = T3;
NET "ddr2_address[9]" IOSTANDARD = SSTL18_II;
NET "ddr2_address[9]" LOC = W2;
NET "ddr2_address[8]" IOSTANDARD = SSTL18_II;
NET "ddr2_address[8]" LOC = W1;
NET "ddr2_address[7]" IOSTANDARD = SSTL18_II;
NET "ddr2_address[7]" LOC = Y1;
NET "ddr2_address[6]" IOSTANDARD = SSTL18_II;
NET "ddr2_address[6]" LOC = U1;
NET "ddr2_address[5]" IOSTANDARD = SSTL18_II;
NET "ddr2_address[5]" LOC = U4;
NET "ddr2_address[4]" IOSTANDARD = SSTL18_II;
NET "ddr2_address[4]" LOC = U2;
NET "ddr2_address[3]" IOSTANDARD = SSTL18_II;
NET "ddr2_address[3]" LOC = U3;
NET "ddr2_address[2]" IOSTANDARD = SSTL18_II;
NET "ddr2_address[2]" LOC = R1;
NET "ddr2_address[1]" IOSTANDARD = SSTL18_II;
NET "ddr2_address[1]" LOC = T4;
NET "ddr2_address[0]" IOSTANDARD = SSTL18_II;
NET "ddr2_address[0]" LOC = R2;
NET "ddr2_dq[15]" IOSTANDARD = SSTL18_II;
NET "ddr2_dq[15]" LOC = F3;
NET "ddr2_dq[14]" IOSTANDARD = SSTL18_II;
NET "ddr2_dq[14]" LOC = G3;
NET "ddr2_dq[13]" IOSTANDARD = SSTL18_II;
NET "ddr2_dq[13]" LOC = F1;
NET "ddr2_dq[12]" IOSTANDARD = SSTL18_II;
NET "ddr2_dq[12]" LOC = H5;
NET "ddr2_dq[11]" IOSTANDARD = SSTL18_II;
NET "ddr2_dq[11]" LOC = H6;
NET "ddr2_dq[10]" IOSTANDARD = SSTL18_II;
NET "ddr2_dq[10]" LOC = G1;
NET "ddr2_dq[9]" IOSTANDARD = SSTL18_II;
NET "ddr2_dq[9]" LOC = G4;
NET "ddr2_dq[8]" IOSTANDARD = SSTL18_II;
NET "ddr2_dq[8]" LOC = F2;
NET "ddr2_dq[7]" IOSTANDARD = SSTL18_II;
NET "ddr2_dq[7]" LOC = H2;
NET "ddr2_dq[6]" IOSTANDARD = SSTL18_II;
NET "ddr2_dq[6]" LOC = K4;
NET "ddr2_dq[5]" IOSTANDARD = SSTL18_II;
NET "ddr2_dq[5]" LOC = L1;
NET "ddr2_dq[4]" IOSTANDARD = SSTL18_II;
NET "ddr2_dq[4]" LOC = L5;
NET "ddr2_dq[3]" IOSTANDARD = SSTL18_II;
NET "ddr2_dq[3]" LOC = L3;
NET "ddr2_dq[2]" IOSTANDARD = SSTL18_II;
NET "ddr2_dq[2]" LOC = K1;
NET "ddr2_dq[1]" IOSTANDARD = SSTL18_II;
NET "ddr2_dq[1]" LOC = K5;
NET "ddr2_dq[0]" IOSTANDARD = SSTL18_II;
NET "ddr2_dq[0]" LOC = H1;
NET "ddr2_ba[1]" IOSTANDARD = SSTL18_II;
NET "ddr2_ba[1]" LOC = R3;
NET "ddr2_ba[0]" IOSTANDARD = SSTL18_II;
NET "ddr2_ba[0]" LOC = P3;
NET "ddr2_rasb" IOSTANDARD = SSTL18_II;
NET "ddr2_rasb" LOC = M3;
NET "ddr2_casb" IOSTANDARD = SSTL18_II;
NET "ddr2_casb" LOC = M4;
NET "ddr2_web" IOSTANDARD = SSTL18_II;
NET "ddr2_web" LOC = N4;
NET "ddr2_clkb[0]" IOSTANDARD = SSTL18_II;
NET "ddr2_clkb[0]" LOC = M2;
NET "ddr2_clk[0]" IOSTANDARD = SSTL18_II;
NET "ddr2_clk[0]" LOC = M1;
NET "ddr2_cke" IOSTANDARD = SSTL18_II;
NET "ddr2_cke" LOC = N3;
NET "ddr2_csb" IOSTANDARD = SSTL18_II;
NET "ddr2_csb" LOC = M5;
NET "ddr2_dm[1]" IOSTANDARD = SSTL18_II;
NET "ddr2_dm[1]" LOC = E3;
NET "ddr2_dqs_n[1]" IOSTANDARD = SSTL18_II;
NET "ddr2_dqs_n[1]" LOC = J5;
NET "ddr2_dqs[1]" IOSTANDARD = SSTL18_II;
NET "ddr2_dqs[1]" LOC = K6;
NET "ddr2_dm[0]" IOSTANDARD = SSTL18_II;
NET "ddr2_dm[0]" LOC = J3;
NET "ddr2_dqs_n[0]" IOSTANDARD = SSTL18_II;
NET "ddr2_dqs_n[0]" LOC = K2;
NET "ddr2_dqs[0]" IOSTANDARD = SSTL18_II;
NET "ddr2_dqs[0]" LOC = K3;
NET "ddr2_odt" IOSTANDARD = SSTL18_II;
NET "ddr2_odt" LOC = P1;
NET "sd_loop_in" IOSTANDARD = SSTL18_II;
NET "sd_loop_in" LOC = H4;
NET "sd_loop_out" IOSTANDARD = SSTL18_II;
NET "sd_loop_out" LOC = H3;

# Prohibit VREF pins on FPGA I/O Bank 3
CONFIG PROHIBIT = H7;
CONFIG PROHIBIT = J1;
CONFIG PROHIBIT = J8;
CONFIG PROHIBIT = L8;
CONFIG PROHIBIT = N1;
CONFIG PROHIBIT = R6;
CONFIG PROHIBIT = T1;
CONFIG PROHIBIT = T6;
NET "sysclk" TNM_NET = "sysclk";
TIMESPEC TS_sysclk = PERIOD "sysclk" 20 ns HIGH 50 %;
NET "ddr2_dqs[0]" CLOCK_DEDICATED_ROUTE = "FALSE";
NET "ddr2_dqs[1]" CLOCK_DEDICATED_ROUTE = "FALSE";
NET "ddr2_dqs[0]" TNM_NET = "ddr2_dqs<0>";
TIMESPEC TS_ddr2_dqs_0_ = PERIOD "ddr2_dqs<0>" 6 ns HIGH 50 %;
NET "ddr2_clk[0]" OFFSET = OUT 7 ns AFTER "sysclk" RISING;
# NET "ddr2_clkb<0>" OFFSET = OUT 8 ns AFTER "sysclk";
NET "ddr2_clkb[0]" OFFSET = OUT 10 ns AFTER "sysclk";
NET "ddr2_dm[0]" OFFSET = OUT 7 ns AFTER "ddr2_dqs[0]" REFERENCE_PIN "ddr2_clk[0]" RISING;
NET "ddr2_dm[0]" OFFSET = OUT 7 ns AFTER "ddr2_dqs[0]" REFERENCE_PIN "ddr2_clk[0]" FALLING;

NET "ddr2_dq[0]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" RISING;
NET "ddr2_dq[0]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" FALLING;
NET "ddr2_dq[0]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" RISING;
NET "ddr2_dq[0]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" FALLING;

NET "ddr2_dq[1]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" RISING;
NET "ddr2_dq[1]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" FALLING;
NET "ddr2_dq[1]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" RISING;
NET "ddr2_dq[1]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" FALLING;

NET "ddr2_dq[2]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" RISING;
NET "ddr2_dq[2]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" FALLING;
NET "ddr2_dq[2]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" RISING;
NET "ddr2_dq[2]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" FALLING;

NET "ddr2_dq[3]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" RISING;
NET "ddr2_dq[3]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" FALLING;
NET "ddr2_dq[3]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" RISING;
NET "ddr2_dq[3]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" FALLING;

NET "ddr2_dq[4]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" RISING;
NET "ddr2_dq[4]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" FALLING;
NET "ddr2_dq[4]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" RISING;
NET "ddr2_dq[4]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" FALLING;

NET "ddr2_dq[5]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" RISING;
NET "ddr2_dq[5]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" FALLING;
NET "ddr2_dq[5]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" RISING;
NET "ddr2_dq[5]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" FALLING;

NET "ddr2_dq[6]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" RISING;
NET "ddr2_dq[6]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" FALLING;
NET "ddr2_dq[6]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" RISING;
NET "ddr2_dq[6]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" FALLING;

NET "ddr2_dq[7]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" RISING;
NET "ddr2_dq[7]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" FALLING;
NET "ddr2_dq[7]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" RISING;
NET "ddr2_dq[7]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" FALLING;

NET "ddr2_dq[8]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" RISING;
NET "ddr2_dq[8]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" FALLING;
NET "ddr2_dq[8]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" RISING;
NET "ddr2_dq[8]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" FALLING;

NET "ddr2_dq[9]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" RISING;
NET "ddr2_dq[9]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" FALLING;
NET "ddr2_dq[9]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" RISING;
NET "ddr2_dq[9]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" FALLING;

NET "ddr2_dq[10]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" RISING;
NET "ddr2_dq[10]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" FALLING;
NET "ddr2_dq[10]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" RISING;
NET "ddr2_dq[10]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" FALLING;

NET "ddr2_dq[11]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" RISING;
NET "ddr2_dq[11]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" FALLING;
NET "ddr2_dq[11]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" RISING;
NET "ddr2_dq[11]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" FALLING;

NET "ddr2_dq[12]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" RISING;
NET "ddr2_dq[12]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" FALLING;
NET "ddr2_dq[12]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" RISING;
NET "ddr2_dq[12]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" FALLING;

NET "ddr2_dq[13]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" RISING;
NET "ddr2_dq[13]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" FALLING;
NET "ddr2_dq[13]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" RISING;
NET "ddr2_dq[13]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" FALLING;

NET "ddr2_dq[14]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" RISING;
NET "ddr2_dq[14]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" FALLING;
NET "ddr2_dq[14]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" RISING;
NET "ddr2_dq[14]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" FALLING;

NET "ddr2_dq[15]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" RISING;
NET "ddr2_dq[15]" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" FALLING;
NET "ddr2_dq[15]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" RISING;
NET "ddr2_dq[15]" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs[0]" FALLING;

TIMEGRP "ddr2_dqs<0>" OFFSET = OUT 7 ns AFTER "sysclk" RISING;
TIMEGRP "ddr2_dqs<0>" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" FALLING;
NET "ddr2_dqs[1]" TNM_NET = "ddr2_dqs<1>";
TIMESPEC TS_ddr2_dqs_1_ = PERIOD "ddr2_dqs<1>" 6 ns HIGH 50 %;
# INST "rddata_afifo_inst" AREA_GROUP = "AG_rddata_afifo_inst";
# AREA_GROUP "AG_rddata_afifo_inst" RANGE = SLICE_X9Y48:SLICE_X0Y79;
# NET "sd_loop_in" OFFSET = IN 1.5 ns VALID 5 ns BEFORE "ddr2_dqs<0>";
NET "sd_loop_in" OFFSET = IN 1.5 ns VALID 7 ns BEFORE "ddr2_dqs[0]";

# NET "ddr2_dq[0]" IBUF_DELAY_VALUE = 1;
# NET "ddr2_dq[1]" IBUF_DELAY_VALUE = 1;
# NET "ddr2_dq[2]" IBUF_DELAY_VALUE = 1;
# NET "ddr2_dq[3]" IBUF_DELAY_VALUE = 1;
# NET "ddr2_dq[4]" IBUF_DELAY_VALUE = 1;
# NET "ddr2_dq[5]" IBUF_DELAY_VALUE = 1;
# NET "ddr2_dq[6]" IBUF_DELAY_VALUE = 1;
# NET "ddr2_dq[7]" IBUF_DELAY_VALUE = 1;
# NET "ddr2_dq[8]" IBUF_DELAY_VALUE = 1;
# NET "ddr2_dq[9]" IBUF_DELAY_VALUE = 1;
# NET "ddr2_dq[10]" IBUF_DELAY_VALUE = 1;
# NET "ddr2_dq[11]" IBUF_DELAY_VALUE = 1;
# NET "ddr2_dq[12]" IBUF_DELAY_VALUE = 1;
# NET "ddr2_dq[13]" IBUF_DELAY_VALUE = 1;
# NET "ddr2_dq[14]" IBUF_DELAY_VALUE = 1;
# NET "ddr2_dq[15]" IBUF_DELAY_VALUE = 1;
#NET "ddr2_dqs[0]" IBUF_DELAY_VALUE = 1;

INST "ddr2_sdram_cont_inst/read_write_io_inst/ddr2_cont_iob_inst/BUFG_inst" LOC = BUFGMUX_X0Y5;

INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_FALL/DPRAM_GEN[15].RAM16X1D_inst" LOC = SLICE_X2Y79;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_FALL/DPRAM_GEN[14].RAM16X1D_inst" LOC = SLICE_X0Y71;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_FALL/DPRAM_GEN[13].RAM16X1D_inst" LOC = SLICE_X2Y71;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_FALL/DPRAM_GEN[12].RAM16X1D_inst" LOC = SLICE_X0Y79;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_FALL/DPRAM_GEN[11].RAM16X1D_inst" LOC = SLICE_X2Y76;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_FALL/DPRAM_GEN[10].RAM16X1D_inst" LOC = SLICE_X2Y68;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_FALL/DPRAM_GEN[9].RAM16X1D_inst" LOC = SLICE_X0Y81;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_FALL/DPRAM_GEN[8].RAM16X1D_inst" LOC = SLICE_X0Y72;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_FALL/DPRAM_GEN[7].RAM16X1D_inst" LOC = SLICE_X0Y65;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_FALL/DPRAM_GEN[6].RAM16X1D_inst" LOC = SLICE_X2Y58;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_FALL/DPRAM_GEN[5].RAM16X1D_inst" LOC = SLICE_X2Y50;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_FALL/DPRAM_GEN[4].RAM16X1D_inst" LOC = SLICE_X0Y54;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_FALL/DPRAM_GEN[3].RAM16X1D_inst" LOC = SLICE_X2Y52;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_FALL/DPRAM_GEN[2].RAM16X1D_inst" LOC = SLICE_X0Y52;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_FALL/DPRAM_GEN[1].RAM16X1D_inst" LOC = SLICE_X0Y60;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_FALL/DPRAM_GEN[0].RAM16X1D_inst" LOC = SLICE_X2Y63;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_RISE/DPRAM_GEN[15].RAM16X1D_inst" LOC = SLICE_X2Y78;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_RISE/DPRAM_GEN[14].RAM16X1D_inst" LOC = SLICE_X0Y70;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_RISE/DPRAM_GEN[13].RAM16X1D_inst" LOC = SLICE_X2Y70;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_RISE/DPRAM_GEN[12].RAM16X1D_inst" LOC = SLICE_X0Y78;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_RISE/DPRAM_GEN[11].RAM16X1D_inst" LOC = SLICE_X2Y77;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_RISE/DPRAM_GEN[10].RAM16X1D_inst" LOC = SLICE_X2Y69;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_RISE/DPRAM_GEN[9].RAM16X1D_inst" LOC = SLICE_X0Y80;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_RISE/DPRAM_GEN[8].RAM16X1D_inst" LOC = SLICE_X0Y73;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_RISE/DPRAM_GEN[7].RAM16X1D_inst" LOC = SLICE_X0Y64;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_RISE/DPRAM_GEN[6].RAM16X1D_inst" LOC = SLICE_X2Y59;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_RISE/DPRAM_GEN[5].RAM16X1D_inst" LOC = SLICE_X2Y51;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_RISE/DPRAM_GEN[4].RAM16X1D_inst" LOC = SLICE_X0Y55;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_RISE/DPRAM_GEN[3].RAM16X1D_inst" LOC = SLICE_X2Y53;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_RISE/DPRAM_GEN[2].RAM16X1D_inst" LOC = SLICE_X0Y53;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_RISE/DPRAM_GEN[1].RAM16X1D_inst" LOC = SLICE_X0Y61;
INST "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_RISE/DPRAM_GEN[0].RAM16X1D_inst" LOC = SLICE_X2Y62;
NET "sd_loop_in_IBUF" MAXDELAY = 1.51 ns;
NET "sd_loop_in_IBUF" MAXSKEW = 0.865 ns;
NET "sd_loop_out" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" RISING;
NET "sd_loop_out" OFFSET = OUT 7 ns AFTER "sysclk" REFERENCE_PIN "ddr2_clk[0]" FALLING;
INST "dcm_CAM_DDR2_clk_inst/dcm_DDR2_clk_dcm" LOC = DCM_X2Y3;

// 02/20 @ 12:48:23
NET "ddr2_sdram_cont_inst/read_write_io_inst/ddr2_cont_iob_inst/dqs_clk_node[0]" ROUTE = "{3;1;3s700afg484;c20d0b8b!-1;-70632;12888;S!0;-159;0!1;-161;-887!"
"2;-1291;-2737!3;-29;-8091!4;259;-695!5;-1703;-139!6;108;53;L!}";
// 02/20 @ 12:51:22
NET "ddr2_sdram_cont_inst/read_write_io_inst/dq_data[0]" ROUTE = "{3;1;3s700afg484;a5bd1784!-1;-70632;26072;S!0;-159;0!1;2447;-605!"
"2;4489;301!2;4489;645!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_inst/read_write_io_inst/dq_data[1]" ROUTE = "{3;1;3s700afg484;751a0e0!-1;-70632;19640;S!0;-159;0!1;1696;1720!2;"
"1784;1376!2;1784;1032!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_inst/read_write_io_inst/dq_data[2]" ROUTE = "{3;1;3s700afg484;89ffb99b!-1;-70632;6136;S!0;-159;0!1;1696;1720!2;"
"1784;1376!2;1784;1032!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_inst/read_write_io_inst/dq_data[3]" ROUTE = "{3;1;3s700afg484;61a7f9cb!-1;-70632;9192;S!0;-159;0!1;2447;-605!2;"
"4489;645!2;4489;301!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_inst/read_write_io_inst/dq_data[4]" ROUTE = "{3;1;3s700afg484;5a9ec78e!-1;-70632;9512;S!0;-159;0!1;1696;1720!2;"
"1784;1376!2;1784;1032!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_inst/read_write_io_inst/dq_data[5]" ROUTE = "{3;1;3s700afg484;c3906147!-1;-70632;5816;S!0;-159;0!1;2447;-605!2;"
"4489;645!2;4489;301!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_inst/read_write_io_inst/dq_data[6]" ROUTE = "{3;1;3s700afg484;3cdde0e5!-1;-70632;19320;S!0;-159;0!1;2447;-605!"
"2;4489;645!2;4489;301!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_inst/read_write_io_inst/dq_data[7]" ROUTE = "{3;1;3s700afg484;48045bde!-1;-70632;26392;S!0;-159;0!1;1696;1968!"
"2;1784;1032!2;1784;1376!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_inst/read_write_io_inst/dq_data[8]" ROUTE = "{3;1;3s700afg484;8152c779!-1;-70632;40144;S!0;-159;0!1;1696;1720!"
"2;1784;1376!2;1784;1032!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_inst/read_write_io_inst/dq_data[9]" ROUTE = "{3;1;3s700afg484;bfa7b4d9!-1;-70632;53328;S!0;-159;0!1;1696;2040!"
"2;1784;1376!2;1784;1032!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_inst/read_write_io_inst/dq_data[10]" ROUTE = "{3;1;3s700afg484;ace04032!-1;-70632;36448;S!0;-159;0!1;2447;-605!"
"2;4489;645!2;4489;301!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_inst/read_write_io_inst/dq_data[11]" ROUTE = "{3;1;3s700afg484;fc333603!-1;-70632;49952;S!0;-159;0!1;2447;-605!"
"2;4489;645!2;4489;301!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_inst/read_write_io_inst/dq_data[12]" ROUTE = "{3;1;3s700afg484;4ce19306!-1;-70632;50272;S!0;-159;0!1;1696;1720!"
"2;1784;1032!2;1784;1376!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_inst/read_write_io_inst/dq_data[13]" ROUTE = "{3;1;3s700afg484;7f7f4c8c!-1;-70632;39824;S!0;-159;0!1;2447;-605!"
"2;4489;301!2;4489;645!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_inst/read_write_io_inst/dq_data[14]" ROUTE = "{3;1;3s700afg484;10d3a509!-1;-70632;36768;S!0;-159;0!1;1696;1720!"
"2;1784;1032!2;1784;1376!3;167;0;L!4;167;0;L!}";
NET "ddr2_sdram_cont_inst/read_write_io_inst/dq_data[15]" ROUTE = "{3;1;3s700afg484;473a4c3d!-1;-70632;53648;S!0;-159;0!1;2479;-949!"
"2;4457;661!3;0;8!3;0;-336!4;167;0;L!5;167;0;L!}";
// 02/21 @ 20:52:31
NET "sd_loop_in_IBUF" ROUTE = "{3;1;3s700afg484;df4ab136!-1;-70632;33392;S!0;-159;0!1;1612;-912!"
"1;1596;1056!1;1680;-1720!1;-1464;-3608!1;-1618;10040!1;-225;1797!1;-1632;"
"-10456!2;-3069;-3647!3;450;5392!3;4355;1359!4;4;-12032!4;4255;-597!5;"
"3927;-4329!5;0;-7000!6;-474;9200!6;178;6576!6;184;13320!7;-1185;4651!7;"
"-1867;-629!8;4111;-10997!8;192;-13688!9;0;-6876!9;3952;222!10;3905;-657!"
"11;2808;3082!11;2917;-5975!11;1152;657;L!11;1152;313;L!12;2123;3408;L!13;"
"-511;-4883!13;1168;-1715;L!13;1168;-1371;L!14;13605;-139!14;-447;-2703!"
"15;24;-6784!16;1099;79!17;-17;-7547!17;-652;-752!18;-658;-744!19;3905;"
"-657!20;1099;-97!21;2976;-3486!22;3935;-4073!22;-652;-752!23;3952;98!24;"
"1152;313;L!24;1152;657;L!25;1152;313;L!25;1152;657;L!26;-2848;-1044!27;"
"-2957;1261!31;-2953;1265!34;-8965;428;L!34;-8965;772;L!35;3935;-4073!36;"
"3935;-4073!37;6944;-24!38;3952;98!39;1099;79!40;1099;79!41;1152;313;L!41;"
"1152;657;L!42;6912;0!43;-2968;104!44;12173;-119!45;1099;79!46;1152;657;L!"
"46;1152;313;L!51;1352;-701;L!51;-2104;-1045;L!52;1352;-701;L!53;1176;"
"-1377;L!56;1152;657;L!56;1152;313;L!57;1152;657;L!57;1152;313;L!58;-2304;"
"313;L!58;1152;313;L!58;1152;657;L!58;-2304;657;L!59;1152;657;L!59;1152;"
"313;L!60;6944;-24!61;6944;-24!64;-2112;-1039;L!65;1160;651;L!65;1160;307;"
"L!66;-7565;776;L!66;-7565;432;L!67;15333;-139!84;1152;657;L!84;1152;313;L"
"!85;-2304;313;L!85;-2304;657;L!91;-7237;772;L!91;-7237;428;L!}";

# CAM_1
NET "cam_clk" LOC = A19;
NET "cam_data[0]" LOC = B17;
NET "cam_data[1]" LOC = A17;
NET "cam_data[2]" LOC = A16;
NET "cam_data[3]" LOC = A15;
NET "cam_data[4]" LOC = B15;
NET "cam_data[5]" LOC = A14;
NET "cam_data[6]" LOC = B13;
NET "cam_data[7]" LOC = A13;
NET "cam_href" LOC = B20;
NET "cam_pclk" LOC = M22;
NET "cam_vsync" LOC = A20;
NET "cam_sio_c" LOC = "C18" | IOSTANDARD = LVTTL;
NET "cam_sio_d" LOC = "A18" | IOSTANDARD = LVTTL;

# CAM_3
# NET "cam_clk" LOC = L19;
# NET "cam_data[0]" LOC = K17;
# NET "cam_data[1]" LOC = K18;
# NET "cam_data[2]" LOC = J18;
# NET "cam_data[3]" LOC = H19;
# NET "cam_data[4]" LOC = G19;
# NET "cam_data[5]" LOC = G20;
# NET "cam_data[6]" LOC = E20;
# NET "cam_data[7]" LOC = F20;
# NET "cam_href" LOC = M18;
# NET "cam_pclk" LOC = L21;
# NET "cam_vsync" LOC = M20;
# NET "cam_sio_c" LOC = "K20" | IOSTANDARD = LVTTL;
# NET "cam_sio_d" LOC = "K19" | IOSTANDARD = LVTTL;


NET "cam_clk" IOSTANDARD = LVTTL;
NET "cam_data[0]" IOSTANDARD = LVTTL;
NET "cam_data[1]" IOSTANDARD = LVTTL;
NET "cam_data[2]" IOSTANDARD = LVTTL;
NET "cam_data[3]" IOSTANDARD = LVTTL;
NET "cam_data[4]" IOSTANDARD = LVTTL;
NET "cam_data[5]" IOSTANDARD = LVTTL;
NET "cam_data[6]" IOSTANDARD = LVTTL;
NET "cam_data[7]" IOSTANDARD = LVTTL;
NET "cam_href" IOSTANDARD = LVTTL;
NET "cam_pclk" IOSTANDARD = LVTTL;
NET "cam_vsync" IOSTANDARD = LVTTL;

NET "red_out[3]" IOSTANDARD = LVTTL;
NET "red_out[3]" DRIVE = 8;
NET "red_out[3]" SLEW = FAST;
NET "red_out[3]" LOC = C8;
NET "red_out[2]" IOSTANDARD = LVTTL;
NET "red_out[2]" DRIVE = 8;
NET "red_out[2]" SLEW = FAST;
NET "red_out[2]" LOC = B8;
NET "red_out[1]" IOSTANDARD = LVTTL;
NET "red_out[1]" DRIVE = 8;
NET "red_out[1]" SLEW = FAST;
NET "red_out[1]" LOC = B3;
NET "red_out[0]" IOSTANDARD = LVTTL;
NET "red_out[0]" DRIVE = 8;
NET "red_out[0]" SLEW = FAST;
NET "red_out[0]" LOC = A3;
NET "green_out[3]" IOSTANDARD = LVTTL;
NET "green_out[3]" DRIVE = 8;
NET "green_out[3]" SLEW = FAST;
NET "green_out[3]" LOC = D6;
NET "green_out[2]" IOSTANDARD = LVTTL;
NET "green_out[2]" DRIVE = 8;
NET "green_out[2]" SLEW = FAST;
NET "green_out[2]" LOC = C6;
NET "green_out[1]" IOSTANDARD = LVTTL;
NET "green_out[1]" DRIVE = 8;
NET "green_out[1]" SLEW = FAST;
NET "green_out[1]" LOC = D5;
NET "green_out[0]" IOSTANDARD = LVTTL;
NET "green_out[0]" DRIVE = 8;
NET "green_out[0]" SLEW = FAST;
NET "green_out[0]" LOC = C5;
NET "blue_out[3]" IOSTANDARD = LVTTL;
NET "blue_out[3]" DRIVE = 8;
NET "blue_out[3]" SLEW = FAST;
NET "blue_out[3]" LOC = C9;
NET "blue_out[2]" IOSTANDARD = LVTTL;
NET "blue_out[2]" DRIVE = 8;
NET "blue_out[2]" SLEW = FAST;
NET "blue_out[2]" LOC = B9;
NET "blue_out[1]" IOSTANDARD = LVTTL;
NET "blue_out[1]" DRIVE = 8;
NET "blue_out[1]" SLEW = FAST;
NET "blue_out[1]" LOC = D7;
NET "blue_out[0]" IOSTANDARD = LVTTL;
NET "blue_out[0]" DRIVE = 8;
NET "blue_out[0]" SLEW = FAST;
NET "blue_out[0]" LOC = C7;
NET "vga_hsync" IOSTANDARD = LVTTL;
NET "vga_hsync" DRIVE = 8;
NET "vga_hsync" SLEW = FAST;
NET "vga_hsync" LOC = C11;
NET "vga_vsync" IOSTANDARD = LVTTL;
NET "vga_vsync" DRIVE = 8;
NET "vga_vsync" SLEW = FAST;
NET "vga_vsync" LOC = B11;
#Created by Constraints Editor (xc3s700a-fg484-4) - 2010/08/03
# NET "clk_cam" TNM_NET = TMN_CLK_CAM;
# NET "clk_ddr2" TNM_NET = TMN_CLK_DDR2;
# TIMESPEC TS_CLK_DDR2_to_CAM = FROM "TMN_CLK_DDR2" TO "TMN_CLK_CAM" TIG;
# TIMESPEC TS_CLK_CAM_to_DDR2 = FROM "TMN_CLK_CAM" TO "TMN_CLK_DDR2" TIG;
NET "cam_pclk" CLOCK_DEDICATED_ROUTE = "FALSE";
# PIN "clk_cam_dcm_inst/DCM_SP_INST.CLKIN" CLOCK_DEDICATED_ROUTE = "FALSE";
NET "cam_href" OFFSET = IN 15 ns VALID 36 ns BEFORE "cam_pclk" RISING;
NET "cam_vsync" OFFSET = IN 15 ns VALID 36 ns BEFORE "cam_pclk" RISING;
NET "cam_data<0>" OFFSET = IN 15 ns VALID 34 ns BEFORE "cam_pclk" RISING;
NET "cam_data<1>" OFFSET = IN 15 ns VALID 34 ns BEFORE "cam_pclk" RISING;
NET "cam_data<2>" OFFSET = IN 15 ns VALID 34 ns BEFORE "cam_pclk" RISING;
NET "cam_data<3>" OFFSET = IN 15 ns VALID 34 ns BEFORE "cam_pclk" RISING;
NET "cam_data<4>" OFFSET = IN 15 ns VALID 34 ns BEFORE "cam_pclk" RISING;
NET "cam_data<5>" OFFSET = IN 15 ns VALID 34 ns BEFORE "cam_pclk" RISING;
NET "cam_data<6>" OFFSET = IN 15 ns VALID 34 ns BEFORE "cam_pclk" RISING;
NET "cam_data<7>" OFFSET = IN 15 ns VALID 34 ns BEFORE "cam_pclk" RISING;
#Created by Constraints Editor (xc3s700a-fg484-4) - 2010/08/08
NET "blue_out[0]" OFFSET = OUT 10 ns AFTER "cam_pclk";
NET "blue_out[1]" OFFSET = OUT 10 ns AFTER "cam_pclk";
NET "blue_out[2]" OFFSET = OUT 10 ns AFTER "cam_pclk";
NET "blue_out[3]" OFFSET = OUT 10 ns AFTER "cam_pclk";
NET "green_out[0]" OFFSET = OUT 10 ns AFTER "cam_pclk";
NET "green_out[1]" OFFSET = OUT 10 ns AFTER "cam_pclk";
NET "green_out[2]" OFFSET = OUT 10 ns AFTER "cam_pclk";
NET "green_out[3]" OFFSET = OUT 10 ns AFTER "cam_pclk";
NET "red_out[0]" OFFSET = OUT 10 ns AFTER "cam_pclk";
NET "red_out[1]" OFFSET = OUT 10 ns AFTER "cam_pclk";
NET "red_out[2]" OFFSET = OUT 10 ns AFTER "cam_pclk";
NET "red_out[3]" OFFSET = OUT 10 ns AFTER "cam_pclk";
#Created by Constraints Editor (xc3s700a-fg484-4) - 2010/08/08
NET "vga_hsync" OFFSET = OUT 10 ns AFTER "cam_pclk";
NET "vga_vsync" OFFSET = OUT 10 ns AFTER "cam_pclk";

#Created by Constraints Editor (xc3s700a-fg484-4) - 2010/08/08
NET "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_FALL/wgray[0]" MAXDELAY = 15 ns;
NET "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_FALL/wgray[1]" MAXDELAY = 15 ns;
NET "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_FALL/wgray[2]" MAXDELAY = 15 ns;
NET "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_FALL/wgray[3]" MAXDELAY = 15 ns;
NET "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_RISE/wgray[0]" MAXDELAY = 15 ns;
NET "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_RISE/wgray[1]" MAXDELAY = 15 ns;
NET "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_RISE/wgray[2]" MAXDELAY = 15 ns;
NET "ddr2_sdram_cont_inst/read_write_io_inst/rddata_afifo_inst/DQS2intclk_FIFO_RISE/wgray[3]" MAXDELAY = 15 ns;
NET "VGAD_Cntrller_inst/camd_afifo_inst/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc[0]" MAXDELAY = 15 ns;
NET "VGAD_Cntrller_inst/camd_afifo_inst/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc[1]" MAXDELAY = 15 ns;
NET "VGAD_Cntrller_inst/camd_afifo_inst/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc[2]" MAXDELAY = 15 ns;
NET "VGAD_Cntrller_inst/camd_afifo_inst/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc[3]" MAXDELAY = 15 ns;
NET "VGAD_Cntrller_inst/camd_afifo_inst/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc[4]" MAXDELAY = 15 ns;
NET "VGAD_Cntrller_inst/camd_afifo_inst/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc[5]" MAXDELAY = 15 ns;
NET "VGAD_Cntrller_inst/camd_afifo_inst/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc[6]" MAXDELAY = 15 ns;
NET "VGAD_Cntrller_inst/camd_afifo_inst/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc[7]" MAXDELAY = 15 ns;
NET "VGAD_Cntrller_inst/camd_afifo_inst/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc[0]" MAXDELAY = 15 ns;
NET "VGAD_Cntrller_inst/camd_afifo_inst/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc[1]" MAXDELAY = 15 ns;
NET "VGAD_Cntrller_inst/camd_afifo_inst/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc[2]" MAXDELAY = 15 ns;
NET "VGAD_Cntrller_inst/camd_afifo_inst/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc[3]" MAXDELAY = 15 ns;
NET "VGAD_Cntrller_inst/camd_afifo_inst/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc[4]" MAXDELAY = 15 ns;
NET "VGAD_Cntrller_inst/camd_afifo_inst/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc[5]" MAXDELAY = 15 ns;
NET "VGAD_Cntrller_inst/camd_afifo_inst/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc[6]" MAXDELAY = 15 ns;
#Created by Constraints Editor (xc3s700a-fg484-4) - 2010/08/11
# NET "Cam_Cntrler_inst/cam_cont_afifo_inst/rgray<0>" MAXDELAY = 15 ns;
# NET "Cam_Cntrler_inst/cam_cont_afifo_inst/rgray<1>" MAXDELAY = 15 ns;
# NET "Cam_Cntrler_inst/cam_cont_afifo_inst/rgray<2>" MAXDELAY = 15 ns;
# NET "Cam_Cntrler_inst/cam_cont_afifo_inst/rgray<3>" MAXDELAY = 15 ns;
# NET "Cam_Cntrler_inst/cam_cont_afifo_inst/wgray<0>" MAXDELAY = 15 ns;
# NET "Cam_Cntrler_inst/cam_cont_afifo_inst/wgray<1>" MAXDELAY = 15 ns;
# NET "Cam_Cntrler_inst/cam_cont_afifo_inst/wgray<2>" MAXDELAY = 15 ns;
# NET "Cam_Cntrler_inst/cam_cont_afifo_inst/wgray<3>" MAXDELAY = 15 ns;
#Created by Constraints Editor (xc3s700a-fg484-4) - 2010/08/11
NET "Cam_Cntrler_inst/cam_cont_afifo_inst/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc[0]" MAXDELAY = 15 ns;
NET "Cam_Cntrler_inst/cam_cont_afifo_inst/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc[1]" MAXDELAY = 15 ns;
NET "Cam_Cntrler_inst/cam_cont_afifo_inst/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc[2]" MAXDELAY = 15 ns;
NET "Cam_Cntrler_inst/cam_cont_afifo_inst/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc[3]" MAXDELAY = 15 ns;
NET "Cam_Cntrler_inst/cam_cont_afifo_inst/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc[0]" MAXDELAY = 15 ns;
NET "Cam_Cntrler_inst/cam_cont_afifo_inst/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc[1]" MAXDELAY = 15 ns;
NET "Cam_Cntrler_inst/cam_cont_afifo_inst/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc[2]" MAXDELAY = 15 ns;
NET "Cam_Cntrler_inst/cam_cont_afifo_inst/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc[3]" MAXDELAY = 15 ns;

# PlanAhead Generated physical constraints 

# BTN_SOUTHをリセットスイッチとして利用する
NET "reset_sw" LOC = "T15" | IOSTANDARD = LVTTL | PULLDOWN ;

# NET "camc_afifo_uf" IOSTANDARD = LVTTL;
# NET "camc_afifo_uf" SLEW = QUIETIO;
# NET "camc_afifo_uf" DRIVE = 4;
# NET "camc_afifo_uf" LOC = U19;
NET "th_disp[1]" IOSTANDARD = LVTTL;
NET "th_disp[1]" SLEW = QUIETIO;
NET "th_disp[1]" DRIVE = 4;
NET "th_disp[1]" LOC = U20;
NET "th_disp[0]" IOSTANDARD = LVTTL;
NET "th_disp[0]" SLEW = QUIETIO;
NET "th_disp[0]" DRIVE = 4;
NET "th_disp[0]" LOC = T19;
NET "tone_mode_disp" IOSTANDARD = LVTTL;
NET "tone_mode_disp" SLEW = QUIETIO;
NET "tone_mode_disp" DRIVE = 4;
NET "tone_mode_disp" LOC = R20;
NET "hand_disp" IOSTANDARD = LVTTL;
NET "hand_disp" SLEW = QUIETIO;
NET "hand_disp" DRIVE = 4;
NET "hand_disp" LOC = V19;
#NET "h_v_is_zero" IOSTANDARD = LVTTL;
#NET "h_v_is_zero" SLEW = QUIETIO;
#NET "h_v_is_zero" DRIVE = 4;
#NET "h_v_is_zero" LOC = V20;
NET "BGR_integ_out[2]" LOC = "W21" | IOSTANDARD = LVTTL | SLEW = QUIETIO | DRIVE = 4 ;
NET "BGR_integ_out[1]" LOC = "Y22" | IOSTANDARD = LVTTL | SLEW = QUIETIO | DRIVE = 4 ;
NET "BGR_integ_out[0]" LOC = "V20" | IOSTANDARD = LVTTL | SLEW = QUIETIO | DRIVE = 4 ;

NET "sw0" LOC = "V8" | IOSTANDARD = LVTTL | PULLUP ;
NET "sw1" LOC = "U10"| IOSTANDARD = LVTTL | PULLUP ;
NET "sw2" LOC = "U8" | IOSTANDARD = LVTTL | PULLUP ;
NET "sw3" LOC = "T9" | IOSTANDARD = LVTTL | PULLUP ;
NET "mode_sw" LOC = "T16" | IOSTANDARD = LVTTL | PULLDOWN ; # EAST SW
NET "th_select_sw" LOC = "T14" | IOSTANDARD = LVTTL | PULLDOWN ; # NORTH SW
NET "hand_sw" LOC = "U15" | IOSTANDARD = LVTTL | PULLDOWN ; # WEST SW

# Controls VCCAUX supply rail (IC19)
NET "aud_l" LOC = "Y10" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = QUIETIO ;
NET "aud_r" LOC = "V10" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = QUIETIO ;